The present invention relates to a method or material of fabricating integrated circuits, and in particular to a method of forming an integrated circuit on a substrate having a low dielectric constant, as well as a polymerizable composition for forming a patterned layer having low dielectric constant on a substrate.
There is a continuing desire in the microelectronics industry to increase the circuit density in multilevel integrated circuit devices, e.g., memory and logic chips, thereby increasing their performance and reducing their cost. In order to accomplish this goal, it is also desirable to reduce the minimum feature size on the chip, e.g., circuit line width, and also to decrease the dielectric constant of the interposed dielectric material to enable closer spacing of circuit lines without an increase in crosstalk and capacitive coupling. Further, there is a desire to reduce the dielectric constant of the dielectric materials such as utilized in the back end of the line (BEOL) portion of integrated circuit devices, which contain input/output circuitry, to reduce the requisite drive current and power consumption for the device.
The most commonly used dielectric material in integrated circuits is silicon dioxide, which has a dielectric constant of about 4.0. Silicon dioxide is readily grown or formed on the surface of a planar silicon wafer that is used to form the majority of the current semiconductor devices. Silicon dioxide has the requisite mechanical and thermal properties to withstand processing operations and thermal cycling associated with semiconductor manufacturing. However, it is desired that dielectric materials for future integrated circuit devices exhibit a lower dielectric constant (e.g., <3.0) than exhibited by current silicon dioxide. As inorganic materials have an inherent limitation to dielectric constants of lower than about three, several types of alternative materials have been developed to achieve lower dielectric constants. A number of these alternative materials are organic polymers, which, if at least partially fluorinated, can have a dielectric constant of less than about three. However, the development of appropriate organic polymers, as well as their depositions and patterning methods, poses significant challenges. The selection or choice of an organic material is frequently limited by the need for higher temperature steps in other aspects of the process, such as metallization or semiconductor fabrication. Another type of alternative material is an inorganic material with dispersed micro voids or pores to achieve a lower effective dielectric constant. Efforts to develop such materials are generally described in J. H. Golden, C. J. Hawker and P. S. Ho, “Designing Porous low-K Dielectrics,” Semiconductor International, May 2001, which is incorporated herein by reference. Further, U.S. Pat. No. 5,895,263, to Carter, et al., which is incorporated herein by reference, teaches a process for forming an integrated circuit device comprising (i) a substrate; (ii) metallic circuit lines positioned on the substrate and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises porous organic modified polysilica.
Although porous inorganic materials can inherently withstand higher processing temperatures, like other dielectric materials, additional challenges arise due to the complexity of the patterning processes. Lithographic techniques are often employed in device micro fabrication. Traditionally, photolithography has been used to define or remove a portion of the dielectric material after it is deposited on the substrate. See S. Wolf et al., Silicon Processing for the VLSI Era, Volume 1—Process Technology, (1986), pp. 407-413, which is incorporated herein by reference. Using microcircuit fabrication as an example, photo resist materials are applied to a dielectric material after deposition on a planar substrate. Next, the resist layer is selectively exposed to a form of radiation. An exposure tool and mask are often used to affect the desired selective exposure. Patterns in the resist are formed when the dielectric layer undergoes a subsequent “developing” step. The areas of resist remaining after development protect the dielectric and substrate regions that they cover. Locations from which resist has been removed can be subjected to a variety of additive (e.g., lift-off) or subtractive (e.g., etching) processes that transfer the pattern onto the substrate surface. However, photolithography has inherent size limitations that demand the use of shorter wavelength sources and more sophisticated optics to reduce the line width and feature sizes in the micro circuitry.
Thus in the process of U.S. Pat. No. 5,895,263 the low-K dielectric layer must be first formed, and then patterned prior to deposition of the conductor material. The plurality of required processing steps inherently increases the processing time, resulting in higher costs as well as generally reduced product yield.
Further, as it is desirable to decrease the size of circuit features, that is line width and spacing between conductors, the alternative inorganic materials must be capable of deposition with pore sizes that are a fraction of the size of these features.
It is therefore a first object of the present invention to provide an improved method of fabricating an integrated circuit device comprising a low dielectric constant material between conductive lines and/or vias.
It is another object of the present invention to provide a process to deposit a patterned low dielectric constant inorganic material on a planar substrate in a minimum number of process steps.
It is a further object of the invention to provide a robust, repeatable process for depositing a patterned low dielectric constant inorganic material.
Other objects and advantages will be apparent from the following disclosure.